The Department of Electronics and Communication Engineering and the Centre for Chip Design, Easwari Engineering College, in collaboration with the Centre for Development of Advanced Computing (CDAC), Ministry of Electronics and Information Technology (MeitY), Chip-In Centre for Chip-to-Startup Programme (Chip-IN), and CoreEL Technologies organizes a Two Days Workshop on SoC Design Flow and PYNQ Python Productivity using ZCU102 and PYNQ Z2.
Dive into the world of Zynq SoCs, IP integrator, Vitis-based embedded system design, and explore Python-based FPGA development using PYNQ, including image processing and machine learning on FPGAs!
Resource Person:
Mr. Siva Subramanian R, Application Engineer, CoreEL Technologies (FPGA Specialist, Xilinx, MATLAB)
Event Highlights:
Date: 23rd & 24th May 2025
Venue: Centre for Chip Design, Electronics Block – I, 3rd Floor, Easwari Engineering College
An incredible opportunity for students, enthusiasts, and professionals looking to build a career in FPGA and embedded systems.
