Two-Day Workshop on SoC Design Flow & PYNQ Python Productivity
The Department of Electronics and Communication Engineering, Easwari Engineering College, in association with Chips to Startup Programme (C2S), MeitY, Government of India, is organizing a hands-on workshop on Embedded System Design using Vitis and Python-based FPGA development with PYNQ. Participants will gain practical knowledge of Zynq architecture, IP integrator, hardware design, and extending embedded systems into programmable logic, along with Python-based image processing, machine learning on FPGAs.
Resourse Person: Mr. Siva Subramanian R, Application Engineer, CoreEL Technologies (FPGA & Xilinx Specialist)
Event Details
Date: 4th & 5th April 2025
Venue: Centre for Chip Design, Electronics Block – 3rd Floor, Easwari Engineering College
Registeration Fee: ₹525/-
Limited seats available!
For further details, contact:
Dr. D. Jessintha: +91 95660 02939
Dr. B. Arivuselvam: +91 99942 01384
Dr. M. Priyadharshni: +91 87546 48342
Event Poster
